1. Field of the Invention
The invention relates to a circuit used in a phase-locked loop (hereinafter referred to PLL) or a delay-locked loop (hereinafter referred to DLL) for detecting phase errors and generating control signals, and more particularly, to a circuit for detecting phase errors and generating control signals through digital processing.
2. Description of the Related Art
A typical PLL may be a digital PLL or an analog PLL. FIG. 1 shows an analog phase detector used in a PLL, and FIG. 2 shows a digital phase detector used in a PLL.
The PLL 10 shown in FIG. 1 includes a phase detector (PD) 13, a charge pump 14, a loop filter 15, and a voltage-controlled oscillator (VCO) 16. The phase detector 13 detects the phase difference between an input signal Fref and a phase-locked clock Fvco and then outputs control pulses Up and Dn according to the phase difference to control the charge pump 14. For example, when the phase of the phase-locked clock Fvco leads the phase of the input signal Fref, the width of the pulse Up output by the phase detector 13 is smaller compared with the width of the pulse Dn to result in a negative control current Icp generated by the charge pump 14. Meanwhile, the loop filter 15 reduces a control voltage Vctl to decrease the frequency of the phase-locked clock Fvco output by the voltage-controlled oscillator 16. On the contrary, when the phase of the phase-locked clock Fvco lags behind the phase of the input signal Fref, the width of the pulse Up output by the phase detector 13 is larger compared with the width of the pulse Dn to result in a positive control current Icp generated from the charge pump 14. Meanwhile, the loop filter 15 raises the control voltage Vctl to increase the frequency of the phase-locked clock Fvco output by the voltage-controlled oscillator 16.
FIG. 2 shows a PLL 20 including a digital phase detector 23, a charge pump 24, a loop filter 15, and a voltage-controlled oscillator (VCO) 16, where the digital phase detector 23 has been disclosed in U.S. Pat. No. 6,259,278. The digital phase detector 23 generates a set of phase error control signals Up1-UpN and Dn1-DnN through digital processing and transmits them to the charge pump 24. Then, the charge pump 24 generates a control current Icp that is to be transmitted to the loop filter 15 for generating a control voltage Vctl. The operating principle of the PLL 20 is the same as the PLL 10, except the signals generated by the digital phase detector 23 are digital signals. Such difference allows a better detection for the PLL 20 to eliminate the dead zone, reduce the clock jitter, and enhance the jitter tolerance of the data random jitter.
However, the output signals of the loop filter 15 of the PLL 20 are still analog signals, and a considerable occupied area is needed for the loop filter 15 since it is a low-pass filter.